#include "HAL_USP_Config.h"
#include "py32f002b_ll_rcc.h"
#include "typedef.h"

void SystemClock_Config(void)
{
  /* Enable HSI */
    LL_RCC_HSI_Enable();
    while(LL_RCC_HSI_IsReady() != 1)
    {
    }

    LL_RCC_SetHSIDiv(HSI_DIV);
    // __HAL_RCC_HSI_CONFIG(HSI_DIV);

    /* Set AHB divider: HCLK = SYSCLK */
    LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);

    /* HSISYS used as SYSCLK clock source  */
    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSISYS);
    while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSISYS)
    {
    }

    /* Set APB1 divider */
    LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);

    /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
    // LL_SetSystemCoreClock(24000000);
    SystemCoreClockUpdate();
}

void EnablePeriphClk(void)
{
    __IO uint32_t tmpreg; 

    RCC->AHBENR = RCC_AHB_PERIPH_CLKEN;
    RCC->APBENR1 = RCC_APB1_PERIPH_CLKEN;
    RCC->APBENR2 = RCC_APB2_PERIPH_CLKEN;

    /* Delay after an RCC peripheral clock enabling */
    tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN);
    UNUSED(tmpreg); 
}
